High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory. In recent years, there has been an effort to further increase the clock speed of memories without sacrificing reliability, which, for a fixed number of clock cycles, effectively reduces an absolute time period available to perform a memory operation. One area of a memory access operation that is independent of the faster clock speeds is the time it takes to charge and discharge access lines during a memory access operation. As clock speeds increase, charging and discharging of access lines may consume an increasingly larger share of allotted time to perform some memory access operations. One time period of a memory access operation that helps define a total latency within a memory to provide data from a memory cell at an output is a minimum row address (RAS) to column address (CAS) delay, or tRCD. The tRCD is a minimum number of clock cycles required between activating a row of memory and accessing a memory cell in a column of the memory cells coupled to the activated row. Reducing the tRCD may provide more time margin for a memory device.